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date: 29 November 2022

Physics-to-Technology Partnerships in the Semiconductor Industryfree

Physics-to-Technology Partnerships in the Semiconductor Industryfree

  • Robert DoeringRobert DoeringTechnology and Manufacturing, Texas Instruments


The development of physics over the past few centuries has increasingly enabled the development of numerous technologies that have revolutionized society. In the 17th century, Newton built on the results of Galileo and Descartes to start the quantitative science of mechanics. The fields of thermodynamics and electromagnetism were developed more gradually in the 18th and 19th centuries. Of the big physics breakthroughs in the 20th century, quantum mechanics has most clearly led to the widest range of new technologies. New scientific discovery and its conversion to technology, enabling new products, is typically a complex process. From an industry perspective, it is addressed through various R&D strategies, particularly those focused on optimization of return on investment (ROI) and the associated risk management. The evolution of such strategies has been driven by many diverse factors and related trends, including international markets, government policies, and scientific breakthroughs. As a result, many technology-creation initiatives have been based on various types of partnerships between industry, academia, and/or governments. Specific strategies guiding such partnerships are best understood in terms of how they have been developed and implemented within a particular industry. As a consequence, it is useful to consider case studies of strategic R&D partnerships involving the semiconductor industry, which provides a number of instructive examples illustrating strategies that have been successful over decades. There is a large quantity of literature on this subject, in books, journal articles, and online.


  • History of Physics
  • Physics and Economics
  • Physics Policy and Management

1. Introduction

As the study of nature at its most fundamental level, physics is in a unique position to bring transformative understanding to humanity’s ability to control his environment. The practical results are typically called “new technology,” often manifested in commercial products that bring heretofore unavailable or impractical capabilities into our daily activities. Because the process of creating technology from physics is a central part of our cultural progress, it is a significant topic. In particular, there are a few generally recognized strategies that have enabled various aspects of this endeavor. The primary goal of this article is to highlight some of the most successful components of such strategies as implemented via partnerships.

Within industry, technology-creation strategy is the domain of research and development organizations. The return on investment from industrial R&D is dependent on optimization of several strategy components, especially the management of risk. An ideal R&D portfolio is balanced between: (1) relatively near-term projects that are driven by new-product schedules requiring development milestones and (2) longer-range research into promising areas via projects that have low-to-moderate estimates for individual success but high payoff from those that do. Thus, a key general strategy for achieving good return on investment from the long-range portion of the portfolio is to increase the number of such projects by sharing their cost and results, within a supply chain including supplier and customers, or even with competitors. Such sharing with competitors is called “precompetitive R&D.” Of course, within a supply chain, what is considered “precompetitive,” may depend on the relative role of a company as a supplier or customer. Precompetitiveness is only one potential strategy element characterizing partnerships between companies and/or other institutions with overlapping interests in cultivating a continuing stream of new physics developments and their engineering into new commercial products.

To appreciate R&D strategies within context, it is useful to focus most of the description on a single physics-based industry example. Arguably, the most appropriate is the semiconductor industry, which is built mostly on a combination of 19th-century electromagnetism and 20th-century quantum mechanics. Some of the considerations behind this choice are:


Many of the pioneering developments were from the efforts of physicists, including Nobel Prize–awarded breakthroughs. In particular, the prizes awarded to Shockley, Bardeen, and Brattain in 1956 for the transistor and to Kilby in 2000 for the integrated circuit (IC) marked seminal developments in the semiconductor industry.


The industry has enjoyed significant sustained growth based on continuing technology advancements over many decades (Semiconductor Industry Association, 2019).


A large fraction of industrial and academic electrical engineering is now based on continuing this development.


Almost every phase of modern life, from how we work to our methods of communication and entertainment, has been and continues to be revolutionized by semiconductor technology, which enables essentially all of electrical/electronics-based devices and systems.

2. The Economic Impact of Physics

In January of 2019, the American Physical Society (APS) published a report entitled The Impact of Industrial Physics on the U.S. Economy (American Physical Society, 2019). Earlier reports of this type from other nations include:

The Importance of Physics on the UK Economy (Institute of Physics, 2012) and

The Importance of Physics to the Economies of Europe (European Physical Society, 2013).

The 2019 APS report estimates that industrial physics directly produced 12.6% ($2.3 trillion) of the U.S. gross domestic product (GDP) in 2016. Total physics-based employment was 45,100,000 jobs. In the same year, industrial-physics-based-sector exports were $1.1 trillion, about 20% of the U.S. total. In the half-century between 1966 and 2016, the constant-dollar, value-added GDP in physics-based sectors increased by a factor of 22, much more than the overall such GDP increase of a factor of 4. From 1947 to 2012, computer and electronic products showed the fastest growth within the eight physics-based sectors. The raw data for this report are from the U.S. Bureau of Labor Statistics, the U.S. Census Bureau, and the Industry Economic Accounts tabulated by the U.S. Bureau of Economic Analyses. Some of the estimations are based on IMPLAN (IMPLAN, 2018), which was developed by the U.S. government in the 1970s and made available for public use in 1991.

As previously mentioned, this article concentrates on the semiconductor-industry example, which is mostly part of the computer and electronic products sector as covered in the 2019 APS report. Specific information on the economic benefit and growth of the semiconductor industry is available in many sources listed in the References and Further Reading sections of this article. In particular, the Semiconductor Industry Association 2019 Factsheet (Semiconductor Industry Association, 2019, May) contains a wealth of current information as well as historical data on this industry. Especially noteworthy in the context of this article is that the semiconductor industry has invested between 15% and 20% of its sales in R&D since 2001. Capital spending (e.g., manufacturing infrastructure) has also remained large.

The next three sections will briefly describe three broad phases of the semiconductor industry, summarizing primary physics developments and their resulting technological and associated economic impact.

3. The Diode Era

The first semiconductor electronic devices were diodes. These are devices with very nonlinear current response to applied voltage. Their early use was primarily as rectifiers, either for conversion of alternating to direct current in electrical power systems or as radio-frequency electromagnetic-wave detectors in “crystal” radios.

During the latter part of this era, the development of quantum mechanics provided basic understanding, via the band theory of solids (Kittel, 1996), of semiconductor diodes and subsequent semiconductor devices. In particular, various forms of “transistors” (discussed in section 4) were developed. Much of the engineering that turned these devices from concept demonstrations in laboratories to practical components was based on a “semiclassical model” (Ashcroft, 1976) of charge (electron and hole) transport in semiconductors that was derived from quantum band structure (Lundstrom, 2000).

4. The Transistor Era

Semiconductor diodes are still important electronic devices, but they are “passive” components. The next great era of semiconductor electronics capability was initiated by the development of an “active solid-state device,” that is, a “transistor” (Burghartz, 2013). Transistors were preceded in this role by vacuum tubes, which also started as diodes, but became active devices via the addition of a gate electrode that allowed control/modulation of the primary current flow through the tube. The gate current is much smaller than the primary current, allowing the active device to be an amplifier or a switch. In principle, active devices allow electronic circuits to address an extremely broad range of applications, which is evidenced in their early use in radios, television, computers, and so forth. However, the practical utility of vacuum tubes in these roles was primarily limited by their relatively low power efficiency and the poor reliability associated with much of the input power being converted to heat. In 1947, physicists William Shockley, John Bardeen, and Walter Brattain demonstrated a type of transistor that led to power-efficiency, reliability, and compactness of electronic circuits far beyond the limitations of vacuum tubes (Bardeen, 1948). In 1956, they shared the Nobel Prize in Physics for this invention (Binhai, 2001). Also in the 1950s, there were several visions of how to make an even greater leap in these metrics by enabling a large number of transistors, as well as passive components, to be tightly interconnected. The “winning” approach that became responsible for the next and largest revolution in electronics, was the invention and demonstration of the “integrated circuit” by Jack Kilby in 1958 (Kilby, 1976). This invention received a share of the Nobel Prize in Physics in 2000 (Binhai, 2001). Kilby’s main insight was that the integration of many components simultaneously manufactured into a monolithic semiconductor “chip” was, in itself, more beneficial at the circuit level than the admittedly better specifications that could otherwise be achieved on separately manufactured components that were subsequently connected (Hoddeson, 1997). The key contribution of the IC concept was in solving the issue of “individual component yield multiplication,” or “tyranny of numbers,” that otherwise limited the overall yield of complex electronic circuits (Glaser, 1977). The integrated circuit has been such a revolution that this technology is still being significantly improved more than six decades after Kilby’s invention (Doering, 2008; Streetman, 2015).

An excellent history of the period from the development of the transistor through the invention of the integrated circuit is available (Hoddeson, 1997). This book is nicely complemented by a 2019 article in Physics Today that describes the related rise to prominence of condensed-matter physics in the post–World War II era (Martin, 2019).

The synergistic growth relationship between the semiconductor industry and condensed-matter physics is a major focus of the present article. In particular, the companies in this industry have clearly recognized the importance of many types of new developments in condensed-matter physics as contributing to new capabilities for integrated circuits. Thus, they have contributed individually as well as collectively to the funding and guidance of a significant fraction of the research in this area. In many cases, this support arises from partnerships that include government funding agencies and programs at federal, state, and even local levels (Wessner, 2003).

5. The Integrated Circuit Era

By coincidence, Richard Feynman gave a presentation entitled “There’s Plenty of Room at the Bottom: An Invitation to Join a New Field of Physics,” at an annual meeting of the American Physical Society (Feynman, 1959), only a little more than a year after Jack Kilby invented the integrated circuit. Feynman was generally speaking about a range of technical possibilities, including for computation, that might result from manipulating matter at the atomic scale via methods beyond conventional chemical synthesis. Thus, although he was not thinking specifically about a potential paradigm for future integrated circuits, he drew attention to a research frontier that was to become the single most important R&D thrust in the integrated-circuit era. This resulted from what has turned out to be the amazing “scalability” of the IC concept, enabling a very long history of continuing improvements, many of them based on revolutions in their own right (Doering, 2008). These improvements are typically characterized by several interrelated metrics:

integration scale

breadth of functionality

cost per function

function performance (e.g., speed/throughput)

energy efficiency

system/circuit compactness

“Integration scale” is basically the number of component devices, typically the transistors, within an integrated circuit. Historically, it has been classified into ranges of integration (Di Giacomo, 1989) and (Chang, 2000), as shown in Table 1.

Table 1. Levels of Integration Scale for ICs

Integration Scale


Transistors Per IC

Small Scale



Medium Scale



Large Scale



Very Large Scale



Ultra-Large Scale





> 109

“Breadth of functionality” refers to the diverse types of electronic functions that might be integrated onto a single IC. Primary functional categories include digital logic, analog signal processing, and memory.

“Cost per function” is the ratio of chip manufacturing cost to some measure of circuit complexity. For example, the latter may be represented by the number of logic gates or memory bits per chip.

“Function performance” could be processing speed in terms of logic operations, memory bits read/written, analog-to-digital-bit conversions, and so on.

“Energy efficiency” is typically some ratio of function performance to the required “active” power. “Standby” power is also often an important metric.

“System/circuit compactness” is typically the ratio of integration scale to the required chip area, for example, transistors or memory bits per cm2.

In large part, all of these improvement trends have been primarily enabled by the single strategy of shrinking component feature sizes, which is called “dimensional scaling” or just “scaling” for short (Luryi, 1999). The vision for this trend has been called “Moore’s Law” (Streetman, 2015; Manocha, 2018). Of course, sustaining it has required increasingly sophisticated research and development across a widening range of individual contributing technologies. Chief among these has been the ability to “print,” which is called “lithography,” the device component patterns at ever smaller sizes (Thompson, 1983). This has been accomplished by R&D across a handful of lithography sub-technologies. Of course, dimensional scaling must be enabled by more than just advances in lithography. It is also necessary that the component devices have excellent and improved electronic performance as they are downscaled. A strategy called “constant electric-field scaling” was proposed by Dennard (Sze, 1998) as an approach to achieving this for Metal-Oxide-Silicon Field-Effect Transistors (MOSFETs), which largely replaced bipolar devices in most IC types during the 1970s and 1980s. Interestingly, the first FETs were explored in the early 1930s by Lilienfeld and others (Streetman, 2015). However, it took many decades before practical versions could be developed (Richman, 1973). As for lithography, the overall approach to transistor scaling quickly became dependent on aggressive R&D across a number of supporting sub-technologies. The physics behind lithography has mostly been optics, as applied to transfering an image from a chrome-on-glass “photomask” to a “photoresist” film on a chip surface. The photoresist changes chemical form in the areas exposed to light, which are then chemically “developed away,” leaving a pattern that is transferred into an underlying deposited film by a subsequent “etch” process. This summarizes the basic IC manufacturing process, in which a stack of patterned thin films is created, typically by “deposit-grow/pattern/etch/repeat” (Thompson, 1983). The mostly optical (pattern-generation) part of this sequence has progressed to smaller component feature sizes via improvements in its sub-technologies, such as through changes in exposure wavelength, numerical aperture, and several forms of diffraction compensation (Doering, 2008).

Thus, IC-level scaling requires an overall hierarchy of technology development, spanning many disciplines, and it is most successful when fed by breakthrough research. In the very early days of IC scaling, good progress could be made in this endeavor largely within the internal R&D efforts of a few, relatively large, semiconductor companies. At that time, the tools used for manufacturing ICs had mostly been developed for other applications, such as other types of lithography and wet-chemistry equipment. As more specialized tools were required, they were first adapted or even designed and built within a few semiconductor companies. The same was true for silicon wafers, IC design-automation tools, IC testers, and so forth. Of course, economy-of-scale soon led to the growth of a separate semiconductor equipment- and materials-supplier industry.

The increasingly complex interdependence of sub-technologies required for IC scaling and their development across more and more companies created opportunities for coordination across the semiconductor industry and with external partners. Next, several types of partnerships will be discussed that have emerged based on models supporting specific business strategies for addressing such R&D needs and their coordination.

6. Industry-Government R&D Partnerships

During World War II, partnerships between government and industry drove much of new discoveries in physics as well as the development of novel applications of physics to the war effort (Glaser, 1977). This was a significant factor in the further development of “central research laboratories,” especially in large companies (National Academies, 2007). Bell Labs was the preeminent example, but GE, RCA, IBM, TI, and quite a few other high-tech- companies had also adopted this research model. These labs hired many Ph.D. physicists, whose work was supported by a combination of internal R&D budgets and government contracts. Their efforts led to numerous new technologies that were very important commercially as well as to national defense. In many cases, the new technologies yielded breakthroughs in scientific instrumentation that enabled new discoveries in physics, thus, representing a powerful feedback mechanism for further scientific and technical progress.

The central-research-lab model faded during the late 1980s and early 1990s, partly as a result of the end of the Cold War with the Soviet Union and the resulting decrease in government research funding in the area of defense (National Academies, 2007). The waning of this model also coincided with a general trend away from the conglomerate diversification strategy. The alternate strategy of “focus on being the best supplier in some market” was becoming widely recognized as a better approach at driving profit margin and shareholder value (i.e., stock price and dividends). Even though it was not initially motivated by this type of change in company strategy, it’s fair to say that the step-wise downsizing/sell-off of Bell Labs, following from the breakup of its parent-company, AT&T, has become most emblematic of the demise of the central-research-lab model.

The semiconductor industry is, again, a good example of this transition. Its postwar development benefited significantly from federal R&D and subsequent electronics-system acquisition contracts. For example, the U.S. Department of Defense was the main customer for early integrated circuits, for example, for Minuteman missile systems (Millis, 2008). National Aeronautics and Space Administration (NASA) soon followed, especially as driven by the electronics development required for the Apollo manned space programs (Wessner, 2003). However, by the early 1980s, the commercial success of the semiconductor industry led to less dependence on government contracts and the necessity for more internally funded research to address market needs that were not completely aligned with federal program requirements. There was even some speculation that the Very High-Speed Integrated Circuit (VHSIC) program of the 1980s (Department of Defense [DoD], 1987) might be one of the last examples of a DoD research initiative that also drove general commercial IC development. The VHSIC program spawned a number of R&D contracts for the development of what is called “1.5-micrometer” N-Channel Metal-Oxide-Semiconductor (NMOS) technology as well as advances in bipolar transistor technology.

Of course, there are motivations beyond R&D for government-industry interaction. One of these led to the creation of a partnership within the semiconductor industry, in the form of a trade association, that soon broadened its agenda and formed a variety of R&D partnerships.

7. Trade Associations, Research Consortia, and Roadmapping

One type of multi-company partnership that may get involved with technology development is a trade association. In the case of the U.S. semiconductor industry, the Semiconductor Industry Association (SIA) was formed in 1977, initially for the main purpose of presenting a coordinated message to the federal government that semiconductor manufacturers in Japan were “dumping” Dynamic-Random-Access Memory (DRAM) ICs onto the U.S. market at prices below cost (Wessner, 2003). Among subsequent initiatives, the SIA then turned to developing an “R&D agenda.” In part, this was driven by the perception that, after projects like the previously mentioned VHSIC, the U.S. Department of Defense was winding down R&D programs on silicon-substrate ICs in favor of more exotic semiconductors, for example, gallium arsenide (GaAs), with larger mobilities. A significant concern was that this would mostly divert government-funded university research in electronics into areas that would probably not have significant commercial impact for a very long time. Thus, the first major result from internal SIA discussion on R&D was the formation of the Semiconductor Research Corporation (SRC) in 1982 (National Academies, 2004). The SRC was founded as a “pre-competitive” consortium, originally of those SIA member companies that were willing to collectively fund and share among themselves the results of university research targeted at results that should have commercial significance within a horizon of roughly 10 years.

The total research scope for the SRC was divided into “thrust areas,” with each member company having one vote in each area on both prioritization of request-for-proposal topics and for selection of proposals to be funded. These votes are cast by Technical Advisory Board (TAB) members in each area. Member companies also have the opportunity to assign liaisons to work with the professors and students on each funded project. The highest level of member company representation is on the Board of Directors (BOD) of the SRC, which is a nonprofit corporation. Each member also has a representative on an Executive Technical Advisory Board (ETAB) that coordinates technical activity below the BOD level, such as developing an overall strategy for balancing the available budget between the individual thrust areas. On an annual basis, this budget is the sum of member-company dues minus a relatively small overhead supporting the SRC consortium infrastructure. The dues of “full” or “limited-engagement” members are dependent on their semiconductor revenues, capped at a value ensuring better balance across company size. It is also now possible to join individual thrusts on a fixed-dues, à la carte basis. The detailed dues model has had a long evolution, as the SRC BOD has attempted to make membership attractive for a variety of companies to create the greatest value for all. This value is obviously based on the “leverage” of sharing research results across multiple funding partners. The SRC research contracts with universities guarantee non-exclusive-royalty-free (NERF) use of the technical results by all eligible SRC member companies. In order to further enhance this leverage, the SRC will often identify results that are worth patenting and pay for such patents on behalf of the universities. This puts such intellectual property into a domain where universities may license it to non-SRC members rather than having it default into public-domain access upon publication in technical journals.

The university research projects typically have a duration of three years, roughly matching the typical Ph.D. thesis research period. Therefore, in addition to the aforementioned IP, part of the research “results” are the graduating students. The SRC goes to great lengths to enhance opportunities for these students to find employment in its member companies.

The next phase of the SIA R&D agenda was to construct a consortium that actually performed shared R&D “in-house” rather than in university labs as in the SRC model. This resulted from a recognition of the increasing Japanese semiconductor prowess, not just the temporary strategy of gaining market share by selling below cost. Another aspect of the threat from Japan was the growing strength of the country’s semiconductor-manufacturing tools and materials companies, especially in the area of lithography, which was synergistic with development of the camera industry in Japan. In particular, Nikon and Canon were becoming dominant suppliers in both markets.

The SIA response was the organization of the SEMATECH consortium (National Academies, 2004). This was a much larger endeavor than the SRC. It was formed in 1987 as a partnership among 14 major U.S. semiconductor companies, who collectively paid dues totalling $100 million annually. This was matched by another $100 million per year from the U.S. Defense Advanced Research Projects Agency (DARPA) over two consecutive five-year contracts. The initial objective was shared development of the next generations of memory technology, as driven by the IC-enabled revolution in computing. In addition to dues, the member companies supported SEMATECH through the efforts of many “assignees,” who relocated from their industry labs to an experimental IC manufacturing facility in Austin, Texas. Physicist Robert Noyce, inventor of integrated circuits manufactured with an adaptation of the “planar process” (Grove, 1967), was selected as the first CEO of SEMATECH. The original objective was soon replaced by a focus on supporting the U.S. semiconductor equipment and materials industry. In part, this was driven by a fear that the U.S. semiconductor makers could potentially be “held hostage” by Japan if they were denied early access to the most advanced manufacturing equipment in favor of their Japanese competitors. The general strategy for SEMATECH became to build consensus on specifications for the next generation of equipment and to solicit corresponding proposals from the U.S. producers. The resulting contracts funded such development, and SEMATECH provided the shared IC manufacturing facility that could provide both an essential development environment and, ultimately, a demonstration showcase for these tools. In this endeavor, SEMATECH inspired the U.S. members of Semiconductor Equipment and Materials International (SEMI), the worldwide trade association for these suppliers, to establish a separate consortium, SEMI/SEMATECH (Wessner, 2003), co-located with SEMATECH, to help coordinate their interaction. After less than 10 years, the members of SEMATECH felt that the consortium’s efforts had demonstrably succeeded, and they decided not to request another extension beyond the second five-year contract with DARPA.

A number of semiconductor R&D partnerships involving industry, government, and/or universities were also started in Europe and, especially in Japan (Wessner, 2003). Of these, IMEC (Europe) and SELETE (Japan) had consortium models that were the most similar to SEMATECH. In particular, SELETE was focused on the development of tools for manufacturing on 300-mm-diameter silicon wafers. This effort inspired SEMATECH to spawn a separate consortium, the International 300-mm Initiative (I300I), which broadened the coordination issues into a worldwide partnership addressing standards, timelines, and other aspects of planning for a leading-edge transition from 200-mm to 300-mm silicon substrates, resulting in approximately a 30% cost savings per cm2 for the most cost-effective, large-scale manufacturing (Chatterjee, 1998; Meindl, 2001).

Near the end of SEMATECH’s first decade, the SIA realized that there was also an opportunity to expand the SRC into programs that could partner with government funding agencies. The first large initiative in this direction was the Focus Center Research Program (FCRP), which was created in 1996 as a separately-managed “sub-consortium” called the Microelectronics Advanced Research Corporation (MARCO) (Wessner, 2003). This allowed for a new membership roster and dues structure, as well as a funding partnership with the DoD. The combined budget was about $30 million per year, split between six focus centers, each winners of a solicitation in selected “focus areas.” Each center had a “lead” university that coordinated the research across multiple universities. The industry-chosen focus areas were intended to address a longer research horizon, with larger resources attacking more fundamental scaling problems than typically addressed by SRC projects.

At this time, it was recognized that the scaling problem could be viewed as separable into research tiers, building from fundamental physics to system electronics design, for example:


device physics


materials science


manufacturing processes


integration techniques


circuit design


system architecture

Of course, enabling synergy between advances in each of these tiers requires coordination for addressing multiple interdependencies. This is essentially another perspective on the aforementioned observation that IC-level scaling requires an overall hierarchy of technology development. Both the SIA and government research-funding agencies were recognizing the need for such semiconductor R&D coordination requirements by the late 1980s.

Over three days in the spring of 1991, the National Advisory Committee on Semiconductors (NACS) and the Office of Science and Technology Policy (OSTP), held a workshop, called MICRO TECH 2000, in which 90 invitees from the semiconductor industry and other organizations were requested to create a recommendation coordinating “road map” for developing an 0.12-micrometer manufacturing process by the year 2000 (National Advisory Committee on Semiconductors, 1991). At that time, this challenge was three years ahead of the scaling trend, an achievement that would enable production of a 1-Gbit Static RAM (SRAM).

Almost simultaneously, the federal government, this time under the auspices of R&D funding agencies, rather than the NACS and OSTP advisory committees, began to plan a separate semiconductor industry road map in partnership with the SIA. The foundational inputs for the new road map were gathered at an even larger workshop, in Dallas, in the fall of 1991. Roughly six months were then spent on finalizing the document, which was then published by the SIA as the National Technology Roadmap for Semiconductors (NTRS) in 1992 (Spencer, 2005). At the time, this was envisioned as a one-time effort, but, inevitably, technology road maps soon get out of sync with actual development, and the NTRS was updated with a second edition in 1994, and a third in 1997. In each edition, the road map horizon was again pushed to cover 15 years into the future of scaling.

The next stage of roadmapping was inspired by the recognition that the scaling challenge had become so large and was being so diversely addressed that it was best coordinated as an international activity. For example, by this time, a large European company, ASML, had joined Nikon and Canon as major suppliers of optical-lithography “exposure” equipment. It had become prohibitively expensive for any U.S. companies to participate in this critical sector of the scaling-R&D race. Thus, the SIA invited four international counterparts, from Japan, Taiwan, Korea, and Europe to join in converting the NTRS into an International Technology Roadmap for Semiconductors, the ITRS, first published in 1999, and, subsequently, at two-year intervals through 2013. A detailed early history and analysis of these road maps is provided in the Ph.D. thesis of Schaller (Schaller, 2004).

During the ITRS period, it became increasingly difficult to build credible consensus on exactly how to scale feature dimensions for another 15 years at the historical average rate of 0.7× per three years, which, amazingly, had actually accelerated during the 1990s to 0.7× every two years. The issue was how to approach the various physical as well as economic “limits” even before devices would need to become “atomic scale.” Around the turn of the millennium, IC limits were frequently discussed in technical publications that complemented and guided the official roadmapping process. Luryi et al. edited a book covering many of the scaling issues (Luryi, 1999). Another example was a special issue of the Transactions of the Institute of Electrical and Electronics Engineers (IEEE). This issue (Meindl, 2001) was edited by James Meindl, a pioneer in the field of IC physical limits. He was also the technical liaison to a contract from the U.S. Army Signal Research and Development Laboratories supporting the work of Jack Kilby for early development of the integrated circuit at Texas Instruments. The individual papers in this issue of the Transactions of the IEEE were written by invited authors with expertise in a range of economic as well as physical limits. Such publications highlighted the fact that not all IC parameters benefited from feature-size scaling and that, at various dimensions, there would not be acceptable tradeoffs between them unless significant new breakthroughs could be discovered in one or more of the IC-research tiers. Due to the excellent efforts of many physicists, engineers, and chemists, such breakthroughs often materialized, overcoming previously predicted limits. One example was a barrier foreseen on MOSFET gate length at about 30 nanometers. This was surmounted mainly by a combination of a new device geometry, the “FINFET,” which changed the electrostatic boundary conditions on FETs, and high-dielectric-constant gate insulators, principally, hafnium-silicon-oxynitride (Doering, 2008). Other breakthroughs included the development of deep-UV lithography, based on excimer lasers and very-large, ultra-high-precision, CaF lenses, to allow exposure wavelengths below 200 nanometers. Today, the very leading edge of optical lithography employs extreme-ultra-violet (EUV—16-nm wavelength) radiation, requiring mirror optics in exposure tools with costs in the range of $50 million to $100 million.

Another factor that changed the perspective of many in the industry on the value and practicality of detailed roadmapping was the realization that scaling limits did not impact all IC products in the same fashion. Digital logic and memory were most improved by scaling, especially to the extent that their main performance attributes, speed and energy efficiency, benefited by feature scaling until the transistors and their interconnect wires became RC-limited in both their speed and heat generation. Of course, analog integrated circuits have additional performance metrics related to noise, dynamic range, linearity, precision, and so on (Horowitz, 1980). This growing part of the IC market needed an optimization path that was significantly different from what had been roadmapped for purely digital circuits. This contributed further to a diminution of consensus on primary drivers for roadmapping. Non-custom-IC value-add was no longer dominated by feature scaling. In fact, the growing cost of integrated-circuit development and manufacturing led to a division of the industry, resulting in a smaller number of traditional semiconductor companies that still both designed and manufactured ICs, a growing number of purely IC-design companies, and a relatively few “silicon foundries” that had been created to manufacture the designs from the companies without fabrication facilities (National Academies, 2008). This change in business model for much of the industry further diminished the desire for continuing participation in detailed pre-competitive roadmapping for many of the U.S. chip makers, which led the SIA to discontinue the original ITRS after the 2013 edition. However, an ITRS 2.0 was subsequently created. Note that most semiconductor companies, even those without fabrication facilities, remain generally interested in continued scaling as long as it leads to a reduction in their costs.

In addition to the diversification of development driven by various categories of integrated circuits, the scaling of semiconductor technology has also resulted in a broader set of interrelated “nanotechnology” R&D agendas and products (Hornyak, 2008). This has provided opportunities for further partnerships and coordinating activities such as the National Nanotechnology Initiative (National Academies, 2016).

8. The Role of Universities

As practiced in an academic environment, physics and engineering are fairly distinct. However, typical career paths from these academic disciplines frequently move into industrial employment, an environment that tends to blur the distinctions. For example, with the evolution from a broader, longer-range research agenda in industrial central research labs to more product-focused R&D, there is a tendency to designate all of R&D staff as “engineers,” regardless of their specific academic degrees. Thus, as seen in the section on the economic impact of physics, it is appropriate to also include the work of all those officially employed as engineers in analyses of contributions from industrial physics. Opportunities for such employment by their graduates are enhanced by university curricula in physics and engineering that include some training or experience in the basics of:

presentation skills

interdisciplinary teamwork


design of experiments

product quality and reliability

risk assessment

legal agreements (e.g., contracts and nondisclosure agreements)


Of course, providing a good education in the basic subject matter of physics and engineering remains the basic role of universities from an industrial R&D perspective. However, in R&D partnerships with industry, the principal activity of universities is usually as research performers. These two roles are very synergistic in graduate-level, for example, Ph.D. thesis, research. Accordingly, the SRC measures its performance with metrics capturing both (1) research results (e.g., reports, publications, and patents) and (2) students graduated. In many cases, the consortium-funded university research also leads to direct-funded research contracts or gifts from industry and to consulting opportunities. In addition, these industry-university R&D partnerships often lead to other types of engagements, such as colloquium presentations from industry and memberships on industry-advisory boards at university, college, and department levels. These boards (or committees) are particularly valuable in guiding universities toward more-effective curricula, research programs, and general goal setting.

9. The Role of Technical Societies

There are also opportunities for technical societies to partner with industry. For the most part, the membership in technical societies consists of individual researchers or managers. However, there are also technical societies that have institutional members, such as other technical societies. The American Institute of Physics (AIP) (American Institute of Physics, 2019) has both types of members and was originally organized as a publisher for physics journals managed by its society members, such as the American Physical Society. For many years, the AIP had a Corporate Associates membership level and an associated Corporate Associates Advisory Committee that selected prize winners in industrial physics, organized Industrial Physics Forums, organized member visits to their corporate labs, and conducted related activities. This Corporate Associates program has been replaced by an AIP Industry Outreach program that still organizes Industrial Physics Forums and provides other opportunities for engagement between academic and industrial physics. The AIP partners with its member societies on the Industrial Physics Forums and other activities. For example, the AIP was one of the funding partners, along with several companies, on the aforementioned APS report The Impact of Industrial Physics on the U.S. Economy (APS, 2019). Note that, although they typically have industrial/applied sections and outreach programs, the U.S. “physics societies” (e.g., most AIP member societies) are primarily managed by and serve their academic members.

From the engineering community, a major technical society involving industry and academia is the Institute of Electrical and Electronics Engineers (IEEE), which is the world’s largest technical professional organization, with over 420,000 worldwide members (IEEE, 2019). It is primarily a publisher of technical journals and a sponsor of technical conferences. It is also the most relevant technical society from the perspective of the semiconductor industry. Many companies will pay for, at least, one technical society membership for their technical employees. This often plays a role in the previously mentioned “transition to engineering” for physicists employed in industry. For example, in choosing a technical society membership to be reimbursed by the company, many physics-degreed professionals will opt for IEEE and, often, drop their APS membership.

All technical societies tend to have good support for students, for example, special memberships, programs, and job-finding activities. They are also typically good partners with industry in building consensus on how the federal government might better help to advance both basic science and technology development. Furthermore, they are also generally effective in partnering with industry, often through trade associations, on delivering messages to both the public and government on research funding, student and work visas, and other issues of mutual interest.

10. Conclusion

This article briefly introduces the types of partnerships between industry, academia, consortia, technical societies, and government that have enabled the effective discovery of new physics and their application to the development of new technologies and the resulting commercial products that have revolutionized our society since roughly the middle of the 20th century.

The first conclusion is that physics has, indeed, contributed greatly to the economies of the United States, European countries, and other nations. The second conclusion is that many forms of partnership can be effective at various points along the “readiness” progression from physics discovery to technology and product development. These partnerships also tend to spawn “spinoff” benefits, such as more effective education, additional opportunities for collaboration, and even better public-policy decisions.

Most of the presentation is in terms of a primary industrial-physics example—the semiconductor industry, especially in the United States. This industry has not only had an exceptionally rapid and sustained history of growth but also an impressive record of converting both fundamental and applied physics research into revolutionary product capabilities.

Note that the Further Reading section includes further recommendations, in addition to the references embedded throughout the text, for reading from sources that should serve as a useful guide to the much broader literature on the theme of this article.

Further Reading

  • Chatterjee, P. (1995). Manufacturing gigachips in the year 2005. Technical Digest of the 1995 Symposium on VLSI Technology, 53–56.
  • Doering, R. (1995). Chickens, eggs, and roadmaps. Solid State Technology, 38(1), 60–61.
  • Doering, R. (2000). Limitations of (and off) the SIA roadmap trends. International Journal of High Speed Electronics and Systems, 10(1), 175–181.
  • Doering, R. (2002). System-on-chip integration. International Journal of High Speed Electronics and Systems, 12(2), 325–332.
  • Doering, R. (2004). Breaking the 2.0-µm barrier. Semiconductor International, 27(4), 61–64.
  • Doering, R. (2011). Potential opportunities for nanotechnology in electronics manufacturing. Solid State Technology, 54(1), 12–15.
  • Hess, K. (2000). Theory of semiconductor devices. Piscataway, NJ: IEEE Press.
  • Hurst, S. (1992). Custom VLSI microelectronics. Hertfordshire, U.K.: Prentice Hall International.
  • McPherson, J. (2010). Reliability physics and engineering: Time-to-failure modeling. New York, NY: Springer.
  • Muller, R. (1977). Device electronics for integrated circuits. New York, NY: John Wiley & Sons.
  • National Academies. (2007). Rising above the gathering storm, revisited: Rapidly approaching category 5. Washington, DC: National Academies Press.
  • National Science and Technology Council. (2003, December). Nanotechnology: Societal implications—Maximizing benefit for humanity.
  • Penney, W. (1972). MOS integrated circuits: Theory, fabrication, design, and systems applications of MOS LSI. New York, NY: Van Nostrand Reinhold.
  • Singh, R. (2002). Issues related to semiconductor manufacturing at technology nodes below 70 nm. IEEE Transactions on Semiconductor Manufacturing, 15(2), 133–136.
  • Sze, S. (1969). Physics of semiconductor devices. New York, NY: John Wiley & Sons.
  • Sze, S. (1983). VLSI technology. Singapore: McGraw-Hill.
  • Taur, Y. (1998). Fundamentals of modern VLSI devices. Cambridge, U.K.: Cambridge University Press.
  • Willardson, R. (2003). Nanoscale electronics for computers and optoelectronics for telecommunications. Cambridge, MA: Academic Press.


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